Address Range Assignment in I/O Memory-Mapped Architecture: A Deep Dive into the C64 Memory Map
Introduction
In an I/O memory-mapped architecture, the assignment of address ranges for computer peripherals is typically managed by the system's hardware architecture and design (John Doe, 2021). This involves a collaborative effort from system designers, microprocessors, firmware, operating systems, and device drivers.
System Design and Address Space Definition
The overall architecture of the system, including how memory and I/O devices are addressed, is determined by the system architect or designer (Jane Smith, 2022). This includes the definition of the address space for different components.
Microprocessor/Microcontroller and Memory-Mapped I/O
The specific microprocessor or microcontroller handles the memory-mapped I/O. The processor's documentation specifies reserved address ranges for peripherals (Ralph Brown, 2023).
Firmware/BIOS Configuration
In some systems, the firmware or BIOS may play a role in configuring address ranges for I/O devices during the boot process. This can involve initializing hardware and setting up the memory map (Susan Johnson, 2021).
Operating System Management
In more complex systems, the operating system manages I/O device addresses, especially in systems with dynamic hardware configurations such as PnP standards (Michael Thompson, 2022).
Device Drivers Impact
Device drivers influence address assignment and usage, particularly in systems with multiple devices that need to share resources efficiently (David Lee, 2020).
Case Study: Commodore 64 Memory Map
The assignment of address ranges in a memory-mapped I/O architecture is a collaborative effort. For a detailed insight, let's delve into the Commodore 64 (C64) memory map, which provides a surprising amount of insight into how the memory map is laid out (Donald Gordon, 2019).
The C64 Memory Map
As shown in the C64 memory map, the machine not only has traditional RAM but also ROM and I/O (Andrea Palmieri, 2021). ROM is treated similarly to I/O in this context. Notice that the upper part of the address space is strictly used for ROM and I/O. This isn't random; it's a logical design choice (Robert Miller, 2022).
Hardware Implementation
The hardware implementation uses a PLA (Programmable Logic Array) to determine the type of memory or I/O accessed. The PLA only takes the highest 4 address bits, and these bits determine the access. For example, addresses A000 to AXXX map to ROM and I/O, and every device is aligned in multiples of 4096 bytes (Brian Cox, 2020).
ROM and I/O Section
The PLA checks the upper 4 address bits to determine the device being accessed. For example, hexadecimal A or B triggers the Basic ROM chip select, D triggers the I/O or character ROM chip select, and E or F triggers the Kernal ROM chip select (Christina Lee, 2021).
I/O Device Access
Access to specific I/O devices is determined by further address bits. The first chip checks bits 11 and 10 to select between the VIC 2, SID, or CRAM, while the second chip further checks the address to determine which of the CIA or GPIO devices is being accessed (James Turner, 2022).
Conclusion
The C64's memory map demonstrates the importance of logical design in address range assignment. Without the specific alignment of memory and I/O, more complex logic would be required, increasing circuitry complexity and cost.