Harvard-Type Processor with Diverse Addressing: A Closer Look at Instruction and Data Memory

Harvard architecture processors have long been a topic of interest in computer science, especially in the context of memory management. The structure allows for separate buses and memory spaces for instructions and data, often leading to more efficient and faster data processing. One question that frequently arises is whether it's possible to have different addressing schemes for instructions and data within the same processor, such as word-addressable instruction memory and byte addressable data memory. This article explores this concept with historical examples and modern implementations.

Historical Examples: Cray Computers

One notable example of a computer with distinct addressing schemes for instructions and data is the Cray computer, particularly the C90. Designed with advanced architecture, the C90 had a unique approach to memory management. Its computer memory was organized into parcels, with instructions stored in a 9-bit format. Branch instructions were managed by referencing these parcels, which required padding to ensure correct timing for memory access.

Despite the complex addressing schemes, the Cray C90 managed to achieve efficient performance through its multi-ported memory system, designed for four-way access. The system had one port for the instruction stream, two ports for data input, and one port for data output. With up to 16 processors, the architecture resulted in a large 64-bit data crossbar switch. However, what set it apart was the separation of instruction access from data access, allowing for more flexibility in how data was managed and accessed.

Modern Implementation: AVR Microcontroller

Modern processors, such as the AVR microcontroller, also demonstrate the feasibility of having different addressing schemes for instructions and data. The AVR microcontroller uses a 16-bit word-addressable program memory (flash) and a byte-addressable data memory. This split addressing scheme becomes more noticeable when programming in assembly language, though it is less relevant in higher-level programming languages due to abstraction layers.

In the context of the AVR microcontroller, the most significant distinction in addressing schemes arises when reading byte data from program memory using the LPM (Load Program Memory) instruction. This instruction requires the use of the Z pointer to point to the byte address in flash memory. However, the flash memory is word-addressable, meaning that the byte address needs to be adjusted accordingly. To achieve this, the Z pointer must be loaded with the byte address, which is twice the word address of the flash bytes.

The process of adjusting the Z pointer can introduce complexities, especially when porting the same code to a different assembler. For instance, the Atmel AVR assembler, with its internal word address counter, demands that the Z pointer be adjusted properly. This means multiplying the word address by two to get the byte address. An example code snippet illustrating this is as follows:

tldittZLlowtable_address2
tldittZHhigh table_address2
...
table_address:
t.db t01 02 03 04 05 ... etc

However, other assemblers like IAR and AS use a byte program counter, meaning they internally handle byte addresses. As a result, when using these assemblers, the address is already in byte format, so there is no need to multiply the pointer address by two. Nonetheless, both assemblers still require that data tables start at an even byte address to ensure no padding is needed for the preceding instructions. This distinction is particularly important when transferring source code from one assembler to another, as additional adjustments to the addresses may be necessary.

Conclusion

Harvard architecture processors showcase the flexibility of having different addressing schemes for instructions and data. Historical and modern examples, such as the Cray C90 and the AVR microcontroller, demonstrate how this approach can lead to more efficient and versatile memory management. While the implementation details can vary, the ability to maintain separation between instruction and data memory significantly enhances overall system performance.